IBM Research and Rapidus co-authored paper accepted at IEDM 2024

Earlier this week at the annual IEEE International Electron Devices Meeting (IEDM) in San Francisco, we shared details on a significant milestone achieved with IBM Research. We unveiled a new chip construction process, called selective layer reductions, that is helping overcome some of the critical challenges to produce 2nm transistors and beyond at scale within the decade.

Scientists from IBM and Rapidus reached a critical breakthrough in consistently constructing chips with a 2nm process. Using two different strategies for selective nanosheet layer reduction, they can now build nanosheet gate-all-around transistors with multiple threshold voltages (or multi-Vt), which allows for chips that can perform complex computations without requiring as much energy. The group found that they could do this without the metal gate boundary problems that tend to accompany this construction method. Check out the findings on the IBM Research blog:https://research.ibm.com/blog/rapidus-ibm-move-closer-to-scaling-out-2-nm-chip-production